The invention relates to a logic analyser comprising means for the detection of a reference combination in a combination of digital input signals selected by a channel selector.
An invention of this type is known from the patent document GB 2,060,182 which corresponds to U.S. Pat. No. 4,375,635 which discloses a logic analyser including a word recognizing arrangement. It includes a certain number of input channels and a word recognizer which enables the detection of a combination of bits which are simultaneously present on the input channels. This document relates more specifically to a possibility to extend the arrangement for combinations which exceed the number of input channels.
Such a logic analyser includes a trigger portion which permits of selecting the useful portion of the signal to be stored and to trigger stopping data acquisition when a certain event occurs. This possibility, called the vertical triggering action since the relevant event is the presence of a predetermined data word during a certain time interval. This triggering action is effected simultaneously on the N input channels.
But said document does not permit of effecting a different type of triggering which might facilitate the use of a logic analyser, namely a horizontal triggering action by means of which it is possible to detect combinations which are characteristic of a faulty functioning of an apparatus to be tested. The problem presented by the invention is therefore to realize a logic analyser which provides the possibility of employing either the vertical triggering or the horizontal triggering at user's option. The triggering action must act on one single input channel and must search for the presence of certain time sequences amongst the flow of input data. To reduce the manufacturing costs, it is furthermore necessary that this object is obtained with a reduced number of components.
The solution of the problems consists in that the detection means supply in accordance with two operating modes a trigger signal when the programmed reference combination is reproduced:
such that, in a first mode, the selected combination is formed by bits appearing at a given instant on different input channels, and, when the input signal combination is maintained during a period of time longer than a first predetermined period, the selector output signal starts a counter, under the control of a clock which is enabled by the output of the selector, in which a target value is loaded which defines the first predetermined value and, when this value has been reached an enable signal is supplied and stored in a first memory means, PA1 and such that, in a second mode, the selected combination is formed by identical bits which appear sequentially on the same channel during a period of time shorter than a second predetermined period, the selector output signal starting the counter in which a further target value is loaded and, when the duration of the selected combination is shorter than the second duration determined by the target value, another enable signal is supplied and stored in a second memory means, PA1 a first logic gate which receives a channel and one of the n bits of a first reference combination, PA1 the output of this first logic gate being connected to the input of a second logic gate which also receives one of the n bits of a second reference combination, one of the reference combinations being intended to select any binary word, the other reference combination being intended to select one of the n channels for forming the channel control channels, the second logic gates assigned to each channel having their outputs connected to a logic gate which effects the AND logic operations of all these outputs to produce the output signal of the selector.
the mode selection being effected at the input with the aid of a channel control signal applied to the channel selector, and at the output with the aid of a mode signal applied to a multiplexer which receives the stored enable signals and supplies the trigger signal.
To effect the channel selection in accordance with the vertical or the horizontal triggering action, the selector comprises, assigned to each channel:
Thus, all the programmed channels will be examined simultaneously to detect whether the reference combination has appeared during a predetermined period of time. Similarly, a single channel could be selected and examined over certain periods of time to detect whether the reference combination has appeared during a period of time less than a predetermined period. For the vertical triggering action the channel selector also effects the word recognition. Its output may be stored in a flip-flop for supply to the multiplexer. For the horizontal triggering action the word recognition is effected by the counter followed by its flip-flops.